Josephson junction logic element

ABSTRACT

Logic elements comprising resettable Josephson junctions cooperating with matched transmission lines have input circuit inductances connected to reversible Josephson devices which are so small that a flux of less than one flux quantum only can be trapped therein preventing the continued circulation of supercurrent in the inductance after removal of the input signals from the associated reversible Josephson junctions. The resettable junctions are designed such that upon removal of the input or control field from the resettable Josephson junctions connected to the transmission line, the a.c. voltage which is generated across said junction, is larger than the timeaverage d.c. voltage across said junction when switched to itss state of normal conductance so that, after removal of the input or control field from said junction, the d.c. voltage is caused to lock back to zero, thus resetting the element. Circuit parameters for achieving resettability without interrupting gate current are given. Logic circuits including AND, OR and NOT circuits are described and the conditions for the operation of such circuits which include both resettable and reversible Josephson devices are also given.

O United States Patent 1 1 [111 3,891,864 Gueret June 24, 1975 JOSEPHSON JUNCTION LOGIC ELEMENT {57] ABSTRACT [75] Inventor: Pierre Leopold Gueret, Thalwil, Logic elements comprising resettable Josephson junc- Switzerland tions cooperating with matched transmission lines [73' Assignee: lmemafional Business Machines have input circuit lnductances connected to reversible Josephson devices which are so small that a flux of Corporation, Armonk, NY.

less than one flux quantum only can be trapped [22] Filed: Nov. 2, I973 therein preventing the continued circulation of supercurrent in the inductance after removal of the input 1 Appl' 412084 signals from the associated reversible Josephson junctions. [30! Foreign Application Priority Dam The resettable junctions are designed such that upon Nov. 17. 1 2 S itze and l6755/72 removal of the input or control field from the resettable Josephson junctions connected to the CL 307/212; 7/277; 7/306; transmission line, the a.c. voltage which is generated 357/5 across said junction, is larger than the time-average l l /0 H03k d.c. voltage across said junction when switched to itss Field Search 307/2l2, 2 state of normal conductance so that, after removal of 17/234 T the input or control field from said junction, the dc. voltage is caused to lock back to zero, thus resetting i561 References Cite the element. Circuit parameters for achieving UNITED STATES PATENTS resettability without interrupting gate current are 3 564 an 2/1971 McCumber 307 300 x give Logic Circuits includirg OR and NOT 3:573:662 4/1971 Fulton 307 300 x Circuits are described and the Conditions for 3,758,795 9/!973 Anacker ct a]. 307/306 operation of such circuits which include both Primary Examiner.lohn Zazworsky Attorney, Agent, or FirmThomas J. Kilgannon, Jr.

resettable and reversible Josephson devices are also given.

5 Claims, 11 Drawing Figures PATENTEDJUN 24 ms SHEET FIG. 1 PRIOR ART FIG. 5

SHEEF PATENTEDJUN 24 I975 FIG. 6

FIG. 7

1 JOSEPI-ISON JUNCTION LOGIC ELEMENT BACKGROUND OF THE INVENTION l. Field of the Invention This invention relates to Josephson Junction devices which. upon removal of an input signal, reset themselves to a zero voltage state without interrupting the flow of gate current. It also relates to Joesphson junction logic elements intended for performing logic functions at high speed. An example for the application of such logic elements is in data processing machines.

2. Description of the Prior Art It has long been a requirement to reduce the time needed in switching operations and to increase the packing density of switching circuits so as to permit the execution of more switching operations in a certain time interval but with a yet smaller space occupied by the switching circuits. The present state of the art encompasses Josephson junction memory elements satisfying these requirements, and it is thus important to include logic circuits which can be manufactured in the same technology.

Switching circuits in Josephson junction technology so far proposed have the severe disadvantage of not being automatically resetting, thus requiring additional switches for their reset operation. While this would not pose a technical problem, the economics of any device incorporating the state of the art switching circuits must suffer considerably through long cycle times.

An example of a state of the art Josephson junction logic element is described in IBM Technical Disclosure Bulletin. Vol. 7, No. 3, August I964, p. 271, by M. F. Merriam. A Josephson junction memory circuit is disclosed in Swiss Pat. No. 486.095. Further references of interest in connection with the invention hereafter to be described are two articles by D. E. McCumber, respectively published in the Journal of Applied Physics. Vol. 39. No. 6, May 1968. pp. 2503-8, and Vol. 39, No. 7. June I968. pp. 3| l3-8, as well as the book, Superconductive Tunneling and Applications, by L. Solymar. Chapman and Hall Ltd., London, 1972.

SUMMARY OF THE INVENTION The present invention in its broadest aspect relates to Josephson junction logic elements having at least one input circuit for coupling at least one input signal to at least one Josephson junction and an output transmission line along which an output signal may be obtained. characterized in that the values of the parameters involved are chosen such that upon removal of the input signals the ac. voltage generated across said junction when in its voltage state becomes larger than the timeaverage d.c. voltage across said junction so as to ensure automatic resetting of the junction to its zero voltage state after removal of the input signals.

In accordance with another broader aspect of the present invention, a Josephson junction circuit having at least a single resettable Josephson junction device therein and. control means electrically coupled to the device and operable during one time period to switch the device from a zero voltage to a voltage state and, during another time period. to reset the device from the voltage to the zero voltage state is disclosed.

In accordance with the broader aspects of the present invention. the control means includes at least a single Josephson junction circuit having at least a single reversible Josephson device therein and at least a single signal means electrically coupled to the reversible Josephson device.

In accordance with more specific aspects of the invention an inductance is utilized which is connected to the reversible Josephson device which has a value such that the maximum flux trapped by said inductance is less than approximately one flux quantum. Where a plurality of reversible Josephson devices are utilized in conjunction with an inductance, AND and OR logic circuits are provided. Also, by the proper arrangement of resettable and reversible Josephson devices a NOT circuit is provided.

In view of the requirements mentioned above and because of shortcomings of the prior art devices, it is an object of the present invention to propose self-resetting logic elements making use of the Josephson effect.

It is a further object of the invention to propose logic elements which are reversible in the sense that the circuits revert back to their original state after removal of the input signals.

The foregoing and other objects, features and advantages of the invention will be apparent from the follow ing more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a state of the art Josephson junction logic element.

FIG. 2 is a diagram of the control gate characteristic of a Josephson junction.

FIG. 3 is an I-V diagram.

FIG. 4 is an [N diagram for a specific output circuit for a logic element.

FIG. 5 is a block diagram of a Josephson junction element with an inductive loop.

FIGS. 6 and 7 show the current transfer in an inductive loop.

FIG. 8 is a circuit diagram of an AND gate.

FIG. 9 is a circuit diagram of another AND gate.

FIG. I0 is a circuit diagram of an OR gate.

FIG. ll is a circuit diagram of a NOT gate.

DESCRIPTION OF PREFERRED EMBODIMENTS The logic elements which are one of the subjects of the present invention employing Josephson junctions make use of two independent principles for controlling their behaviour. In order that these principles become more readily understandable and in order to provide one skilled in the art with data useful to the execution of the invention to be described, a brief consideration of prior art devices appears desirable.

A terminated logic element consisting of a Josephson junction connected to a matched transmission line has already been proposed. Such an element is shown in FIG. 1 where 10 is a Josephson junction with its conductance G and capacitance C, shunted by a transmission line H having a characteristic impedance Z,,. The transmission line I] is terminated by a resistance R,, that matches the characteristic impedance Z,,. The parallel circuit of Josephson junction 10 and transmission line 11 is fed with a bias current I], on a line 12. Coupled to Josephson junction 10 is a control line 13 to which a control current b may be applied. By proper design. control current L controls the value of the maximum current i,,, through the Josephson junction by means of the magnetic field which it generates. This is explained by reference to the control gate characteristic of the Josephson junction in FIG. 2.

FIG. 2 shows a typical example of the dependence of the maximum Josephson current i on the control current. I... Wit L. O, a certain value i,,,,, can flow in the Josephson junction which is basically a function of the materials used and the dimensions of the junction. At current levels above i,,,.,, the Josephson junction will spontaneously switch from its zero voltage state to its voltage state. As the control current l,- is increased, for example to the value I,-,. the maximum Josephson current before switching is reduced to i,,,,.

In the superconducting state of the Josephson junction. all of the bias current 1,, is flowing in the junction (l,,=l because the terminated transmission line 11 represents a resistive path. It now a control current L is applied. the Josephson junction will be switched to its voltage state. and a voltage drop V occurs across the junction. Now the bias current l will be split into a part I 1,, continuing to flow through the Josephson junction and a part I, transferred into the load resistance R, with I, V /R The corresponding operating point is graphically obtained in FIG. 3 wherein curve A gives the characteristic of a Josephson junction with no control circuit l,. applied. The maximum Josephson current is at i,,,,,, the bias current I,, thus being lower than i,,,,,. Initially, all of this current flows through the Josephson junction. With a control current l.- applied to control line l3 (FIG. 1), the maximum Josephson current is reduced from i,,.,, to i,,,,. and the characteristic is transferred from curve A to curve B. Now that the bias current I is larger than the maximum current i,,,,. admitted, the Josephson junction switches to its voltage state and assumes the operating point F at the intersection of the load line 14 with curve B. The current l,. is now divided into a current l, continuing to flow through the Josephson junction and a current I through the load resistance R, The voltage drop over the Josephson junction is V When the control circuit 1,. is afterwards removed, the characteristic B reverts back to curve A and the operating point moves from F to P. The position of P depends on I Z and the junction hysteresis characteristic through parameter B. wm'C/G where w", HA/h, A is the superconducting gap and G is the normal conductance for voltages V,,. As can be seen in FIG. 3, one ends up with currents l and I, flowing respec tively in the branches of the circuit, and a finite voltage V, across the junction. The circuit obviously has not reset.

in order that the circuit be enabled to reset entirely, i.e., reverting to the initial condition of zero junction voltage with all of h, flowing through the junction, it is necessary to momentarily switch off the bias current l,,. thus allowing the junction voltage to lock back to its zero value. In other words, for resetting. the bias current 1,, has to be pulsed. This is a great disadvantage of the prior art devices because. if it is desired to stack a number of the circuits just described, it is mandatory to isolate them from one another by inserting large inductances in the common bias line so that switching occurring in one circuit does not affect any of the other circuits. If for reset the bias current l would have to be switched off. all of the circuits on that line would be affected anyway and. it would take a very long time until the energy stored in the inductances vanishesv By proper design. it is possible to obtain a selfresetting circuit without any need for pulsing the bias current I This circuit makes use of the dynamic properties of the Josephson junction. namely of the fact that when there exists a finite static (time-average) dc. voltage 5 V across the Josephson junction, an a.c. voltage V of the frequen y f; I 26/): V appears which is superimposed on V, (a.c. Josephson effect)v The amplitude of the a.c. voltage V depends on the junction properties as well as on the load across it.

It is known that a Josephson junction which has been driven into the voltage state returns automatically to its zero voltage state once the total junction current I becomes smaller than some minimum value l,,,, This phenomenon is a dynamic one and is a direct consequence of the a.c. Josephson effect. It occurs actually when the instantaneous junction voltage V V crosses the line V,, O. The actual junction voltage V for which this occurs is the minimum voltage inin- In order to obtain a self-resetting circuit, one has, therefore, to design the Josephson junction and the circuit parameters such that in the absence of input signals. the junction lV characteristic and the load line have only one stable point in common, namely that on the zero voltage line.

In the circuit of FIG. 1 with 1,. =0. a finite average voltage V gives a Josephson current I i,,,, sin w where 111 211': V This current which flows through the parallel combination of G, C and 2,, gives rise to an a.c. voltage V of an amplitude lVI in accordance with:

For automatic resetting. the junction current l must be l,,,,',, as discussed above and written in equation (3) At the point s (FIG. 3) the amplitude W of equation l is equal to V,,,,-,, and V locks to zero. The criterion for self-resetting is obtained by using 2.5/0. wherein V is the gap voltage chosen to be V 2.5mV. A 210 Ws is obtained. With these values it is now possible to calculate the Josephson frequency at the gapf, rrA/h which is found to be f,,, 0.95'10 5" This result permits the computation of the admittance ratio [3, m,,,C/G,, and this is found to be B,

Taking then B l which corresponds to a maximum Josephson current density ofJ,,,,,,,- 2.310 A/cm'-'. with G/G,, 0.2, and for no control current I. applied, i.e., i i,,,,,, equations (4a) and (4b) yield respectively min- /i,,,,, 0.5 l and V,,,,-,, 2 mV. Equation (4c) yields then (l,,/i,,,,,) 0.76 as the requirement for self-resetting with the data given above. Taking (l,,/i,,,,,) 0.7, i.e.. 057 in agreement with equation (5) with G,,Z, G,,R, 4, which is the condition for VJ to be in the vicinity of the gap voltage V it is now possible to determine the relation between the transferred current I, in the load resistance R, and the bias current 4 Tr (I+Z,,G) (5) With equation (7) one obtains i,,,/i,..,, 0.9.

For the case with control current present (I,- r such that I' /i 0.3, we have X,,,;,, 0.55 (V Li mV) with equation (4b), and I,,,.-,,/i,,,,, 0.14 with equation (4a).

With the above-made assumption of a current density of 1",, 2.3.10 A/cm the maximum Josephson current becomes i,,,., 0.92 mA. hence the bias current 1,, 0.64 mA. A circuit with the parameters as proposed above will be self-resetting after the removal of the control current I,..

FIG. 4 shows the I-V characteristic of a Josephson junction using the data of the example given above.

It is of course important to choose the circuit parameters appropriately in view of the purpose which the circuit should serve. If the circuit were to be combined with others to perform some logic function, and the other circuits also contain Josephson junctions which are to be controlled. e.g.. by the current I, transferred into the (terminated) line of the first circuit upon switching. that current I must be of sufficiently large magnitude to cause switching of the further Josephson junctions. This naturally depends on the properties of the Josephson junctions involved.

A combination of this self-resetting circuit with another Josephson junction circuit which will be described results in a scheme for logic elements in accordance with the present invention. Consider now a circuit such as that of FIG. 5 in which the right branch is an inductance L. The current conditions and the phase d) across Josephson junction are described by the equation Ina/ nto lll lllll Sin 4 wherein i, is the maximum Josephson current for l.- 0 and A=wmLGn=21rN. where N is the maximum number of flux quanta 1)., which can be trapped in the inductance L.

5 The solution of the equation for the currents in the circuit of FIG. 5 can be obtained graphically as shown in FIG. 6. A straight line 16 represents that part of the current which is linear in d) i.e., the current l /z' 051A flowing in the inductance. and a sine wave I7 superimposed on the straight line 16 represents the current I i,,, sin d: in the Josephson junction. With a bias current I,,,, applied to the circuit of FIG. 5, an operating point D is obtained. At this point, a rather large part 1', of the current I,,,, flows through junction 15, whereas only a small amount of I, is allowed to pass through the inductance L.

As has been mentioned before, the application of an external magnetic field to the Josephson junction by means of a control current I,. brings about a reduction of the maximum Josephson current i,,,,,. In connection with the circuit of FIG. 5, this fact is manifested by the dashed sine wave 18 in FIG. 6. Application of the control field, therefore. will result in the shifting of the operating point from D into D. As can be seen from FIG. 6, the current relations have changed in that there is If the inductance L is chosen small enough, the slope of the straight line 16 in FIG. 6 will be large so that the sine wave 17 superimposed thereon never crosses the b-axis. The determining factor is the value of A. To avoid any crossings other than zero point, one must have A 311/2. If, however, the inductance L were large. the slope of line 16 would be small. and accordingly, the sine wave could have multiple intersections with the rib-axis. This situation is shown in FIG. 7. If the current is initially increased, the operating point follows the sine wave 17' to point T, where the Josephson junction switches and a transfer to point T;- occurs. If the current is then decreased, the operating point follows the sine wave 17' to point T;, which is a stable point of operation. At this point. a current I, continues to circulate in the loop with zero current supplied from the outside. Actually. this case is the basis for a Josephson memory cell which. however. does not form part of the present invention.

In contrast, the present invention is devoted to a scheme where the inductance L is small enough that except for the zero point there are no intersections of curve 17 with the rib-axis. According to FIG. 6, this occurs providing A 31r/2. Since A 21rN. this is equivalent to N 3/4. In other words. the inductance must be small enough that the maximum flux L i is less than approximately one flux quantum l Under these conditions, no circulating current can possibly remain in the loop when the external sources are removed. This can be seen in FIG. 6 where initially increasing the current will lead to point U where the junction switches to point U from which the sine wave 17 is followed to point U from where the junction switches back to point U to return to zero point.

Returning now to the conditions earlier mentioned in connection with FlG. 6. i.e., with a control current l,. applied, and with a bias current l flowing into the circuit. operating point D is assumed. A larger current is now flowing in the inductance L. whereas a reduced current remains flowing in the Josephson junction. Since conditions are chosen so that no switching of the junction (15) occurs in this process. the operating point will return from D to D upon removal of the external field generated by the current I... and the current distribution is again what it was originally. The current transfer process brought about by the external control current l,. is thus fully reversible.

The flux l in the loop of FIG. 5 containing the inductance L is given by D1. (tb/Zrr) I It can be seen from FlG. 6 that the maximum reversible" flux which can be trapped in the loop obtains for D 11' and is equal to 42 /2.

in case the circuit arrangement of which the circuit of FIG. is only a part. requires an operation with larger values of 1 it is necessary to start out with larger values for the bias current h In general. if one takes 2N rrlk lawlinm (2N +1) rr/A. reversible current transfer can also be achieved by controlling r',,.. The trapped flux 1 varies then between N i and (N 1/2) 4%.

The two concepts of self-resetting circuits and of reversible current transfers described in the previous paragraphs are used in what follows to realize various ele ments for performing certain logic functions. such as AND. OR, NOT. With these concepts realized in their design. all of these elements always revert automatically to their initial state once their input signals are removed. Under these circumstances, the operating conditions are unique and well defined. Moreover, there is no need for pulsing the bias sources. allowing, therefore, for shorter cycle times.

FIG. 8 shows an example for a three-input AND gate in accordance with the present invention. This AND gate consists of an input circuit 19 comprising the Josephson junctions 20 through 22 in parallel connection which are supplied by a common bias line 23 to which the bias current I,,., is applied. Josephson junctions 20 through 22 can be controlled by applying appropriate currents L, through I, to their respective control lines 24 through 26. Also in parallel connection with Josephson junctions 20 through 22 is an inductance 27.

The AND gate also comprises an output circuit 28 having a Josephson junction 29 connected to a bias line 30 and a transmission line 31 with a characteristic impedance Z Transmission line 3] is terminated by a load resistance 32 of the value R Z,,.

This AND gate is designed such that an output current I, is obtained only if all of the input currents i through L are present. The AND gate will automatically reset (with l, 0) if at least one of the input currents 1.. L or I. is removed.

With the three input currents 1,. through L present. most of the bias current I is transferred into inductance 27 as control current I. The magnetic field gen erated by this control current I,- will reduce the maximum Josephson current i,,, of the neighboring Josephson junction 29 below the value of the bias current I im" (at!) and with the condition i,,, l,,. the condition In/i,,,,, 0.64 is obtained for switching junction 29 in the presence of all of the input currents L, through L.

On the other hand, no switching should occur is only (n-l) of the :1 inputs of input circuit 19 are energized. Again using equation (8a) and FIG. 6, this additional requirement leads approximately to I,./i,,.., 0.9. The conditions for l,, are summarized in equation l0) The condition for self-resetting is given in equation (4c). The conditions for the input circuit 19 are summarized in equations (9a) and (9b).

O I A (N=O) (9a) Equation (9a) refers to the fundamental mode (N=O). For a practical embodiment of an AND gate one starts with the determination of the parameters for the output circuit 28. The values J,,,,,,=2.3 lOA/cm A 4 12m 0,, 0.47 i). Z 4.2 I (G,,Z,, 2). G/G 0.2 and [3,. l with equation (4c) give l,,i,,,,, l .0 as condition for self-resetting. With equation 10) the limits are 0.64 l,,/i,,,,, 0.9. If one chooses l,,/i,,,,, 0.8. one obtains lljl i 0.8 with equation (6). and with equation nt/ nn:

it is now necessary to calculate the control current l,v which is to flow in the inductance 27 of the input circuit l9. The value i,,,/i,,,., 0.8 found for the output circuit implies with equation (8a) that I 0.36. Using equation (8b) lllli llllhr A=2.3- lO*A/cm '4 l0"cm"-=0.92 mA. and thus .05 mA is found.

if it is now assumed that when all inputs 24 through 26 are energized. about of the input bias current i,,,, is transferred into inductance 27, one must then have I,=0.9-l,,,, which gives I, 2.3 mA. Taking then A=1r to satisfy equation (9b), equation (9a) gives l,,,,/i,,,,, l for the input circuit or i,,,, I,,,,= 2.3 mA for the junctions in the input circuit. With i,,, .Imur'A and for Jrnur 2-3'I0 Alcm one finds A cm, i.e., the area of the input junctions -22 should be larger than 10" cm (for example= 3 pm X 4 pm).

Another way of implementing an AND gate is shown in FIG. 9. In this implementation input circuit 19 and output circuit 28 of the AND gate of FIG. 8 are com bined to a common circuit 33 driven by a single bias current I,,. Josephson junctions 34 through 36 are respectively in series connection with inductances 34 through 39. Each of the junctions has its own control line 40 through 42, to which lines control currents I through can be applied. The brancehes with Josephson junctions are in parallel connection and hooked to a transmission line 43 which is terminated by a resistance 44 whose value corresponds to the characteristic impedance Z, of line 43.

In operation, voltage V, V is expected to appear across resistance 44 if all n inputs of the AND gate carry their input currents i,,, i.e., the Josephson junctions 34 through 36 must all have switched to their voltage state. If only (n-l) or less inputs are energized, no switching should occur, currents being transferred (in accordance with the same principle as described in connection with FIG. 6) into the non-energized branches.

These requirements lead to the condition lllIl) h/ "|0) |u/ |lv'fl) i where A ru LG 2-n'N. For complete reversibility, the inductances 37 through 39 have to be small enough that no loop current is allowed in the circuit after removal of all input signals. This implies 2A 3 rr/2, i.e., the inductances must be so small as to be able to trap only a fraction of one flux quantum l Under these conditions. circuit 33 operates as a reversible AND gate. In addition, it is self-resetting if (G,,Z,,) and B,- are chosen small enough as required by equation (40). In a preferred embodiment, the following parameters yield a reversible, self-resetting threeinput AND gate:

An example of an OR gate using similar principles as the AND gate of FIG. 8 is shown in FIG. 10. In this example. three Josephson junctions 45 through 47 are in series connection with a bias line 48 and operate on a common inductance 49 which is connected in parallel to the junctions. Each of junctions 45 through 47 has its own input line 50 through 52, respectively. Inductance 49 is coupled to a Josephson junction 53 having its own bias line 54. As in the circuit of FIG. 8, junction 53 is connected to a transmission line 55 which is terminated with a resistance 56 of the value R Z The OR gate will deliver an output signal (and a voltage V, V across resistance 56) if any one or more of the input currents I, through I are present. In this case, the respective Josephson junction 50, 51 or 52 is, for example. driven from an initial operating joint at D in FIG. 6 to a new operating point at D, owing to the fact that the sine wave 17 for L, in." sin d) has been flattened to the smaller sine wave 18 with I i,,, sin d). As can be seen from FIG. 6, at point D' a larger part of the bias current I,,,, has transferred into inductance 49. Care must be taken, however, that the application of the input currents I, to input lines 50 through 52 does not cause associated Josephson junctions to switch.

The application of one of the input current I, should result in an increased control current L- in inductance 49 of a magnitude sufficient to reduce the maximum Josephson current i,,, in junction 53 so that the latter switches to its voltage state, thus transferring part of the bias current I,, into transmission line 55.

With these premises the operating conditions for an OR gate are as follows: The reversibility of the input circuit 57 is ensured if l/m/i,,,,, 1r/A. Assuming a gate characteristic as in equation (8a), switching ofjunction 53 in output circuit 58 when one input current I,- is applied, requires that l,./i,,,,, 0.64. Self-resetting of output circuit 58 is guaranteed, if equation (4c) is satisfied. One obvious advantage of the proposed OR gate is that, in spite of the input junctions 45 through 47 all being in series, the output current is always a constant =V /R One possible implementation for a NOT gate is shown in FIG. 11. The NOT gate is to deliver an output signal (and a voltage drop V across its output resistance R,) if the input signal I is not present. The NOT gate has an input circuit 59 comprising a Josephson junction 60 and two inductances 6] and 62 in parallel connection, one of them (61) being connected in series with junction 60. Bias current I is applied to a bias line 63 of input circuit 59 and is divided to flow in substantially equal parts through both branches 64 and 65 of input circuit 59. Josephson junction 60 has an input line 66 to which an input current I, can be applied.

With no input current I, present, bias current is distributed between branches 64 and 65 as mentioned. The control flux D.- L i,,,/2 flowing in branch 64 which contains junction 60, is used to control a Josephson junction 67 of output circuit 68. Control flux 1 is made large enough to keep junction 67 in its voltage state, thus producing a voltage V across resistance 69.

If an input signal I, is applied, the maximum Josephson current of junction 60 is reduced and most of the current L. is transferred from branch 64 into branch 65. The transfer is reversible and occurs without switching of junction 60 in a way which has been described in connection with FIG. 6. The remainder of the flux (1 does not then suffice to keep Josephson junction 67 in its switched state, and hence the output circuit 68 re- Sets with V, O.

The reversibility of this NOT gate is ensured if with A being proportional to the inductance L. With N O (so-called fundamental mode) and a gate charac teristic in accordance with equation (8a) assumed. one has O I,,,,/i,,,,, rr/)\, and Josephson junction 67 of output circuit 68 switches if I,,/i,,,,, 0.9.

For the case N 1, input circuit 59 is operated with 21r/A (l,,,,/i,,,,,) 31r/.\, and junction 67 will be in its voltage state (when I, 0) providing l,,/i,,,,, 0.35.

It should be very clear to one skilled in the art to expand the principles of reversibility and self-resetting beyond the examples herein given to logic circuits performing other functions. without departing from the spirit of the invention.

What is claimed is:

1. A Josephson junction logic circuit comprising an output circuit having at least a single resettable Joseph son device connected to a transmission line which is terminated with its characteristic impedance and having an input circuit coupled to said device. said output circuit having parameters which meet the following criterta:

1 'm/1,... 1 1.. a. 2a 4 1/2 1r VI, [3,.

t. (:14 F MGR.

2a QR, Va.

wherein l,,,;,, and V...,-,. are. respectively. the minimum junction current and voltage beyond which said junction reverts to its voltage state. l... and i,,, are. respectively. the maximum Josephson currents for I,- O and l,. I U. G is the actual conductance at V G is the normal conductance for V V V is the gap voltage. V is the voltage drop across said Josephson device. l,, is the bias current supplied to said junction. B.- the junction admittance ratio. R is the output resis tance and l,. is the control current applied to said input circuit. said input circuit including at least a single reversible Josephson device therein and at least a single signal means electrically coupled to said at least a single reversible Josephson device and at least an inductance electrically connected to said at least a single reversible Josephson device. said inductance having a value that. at least in the fundamental mode. where N 0. only less than one flux quantum can be trapped by said inductance and wherein l,,,,/i,,.,, Ir/A where l,,,. is the bias current supplied to said reversible device. A is proportional to the inductance L and. N is the maximum number of flux quanta. d)... which can be trapped in the inductance.

2. A Josephson junction logic circuit according to claim I, further including another inductance connected in parallel with said input circuit. the current through said input circuit controlling said at least a resettable Josephson junction. both of said inductances being connected to a source of bias current. said input circuit and said another inductance having parameters such that. in the absence of a signal from said signal means. said bias current is divided between said inductances resulting in a control current sufficient to keep said resettable Josephson junction in its voltage state. thereby generating an output in said transmission line and. such that. upon application of a signal from said signal means. current in said input circuit is reduced to a value insufficient to maintain said resettable Josephson junction in its voltage state. causing said resettable Josephson junction to switch to its zero voltage state. thereby eliminating an output signal in said transmission line and wherein the logic circuit parameters to en sure reversibility meet the conditions:

3. A Josephson logic circuit according to claim 1. wherein said input circuit includes a plurality of reversible Josephson devices electrically connected therein.

a plurality of signal means each one of said signal means being electrically coupled to a reversible Josephson junction device.

at least an inductance electrically connected to said plurality of reversible Josephson devices, said inductance having a value that. at least in the fundamental mode. where N 0, only less than one flux quantum can be trapped by said inductance and wherein l,,,,/i,,,., 1rl where l,,,, is the bias current supplied to said reversible junctions. it is proportional to the inductance L and. N is the maximum number of flux quanta. d which can be trapped in the inductance.

4. A Josephson logic circuit according to claim 3. wherein said plurality of reversible Josephson devices are disposed in parallel in said input circuit. and said inductance is connected in parallel with said plurality of reversible Josephson devices. and has a value such that the current flowing therethrough when all of said plurality of signal means are energized assumes a magnitude sufficient to switch said at least a single resettable Josephson junction under the conditions:

for said input circuit. where 3 A Tn and for switching said resettable device when all of said signal means are activated and for maintaining said resettable device in an unswitched state when at least one less than all of said plurality of signal means are activated. respectively.

5. A Josephson logic circuit according to claim 3. wherein said plurality of reversible Josephson devices are disposed in series in said input circuit and said inductance is disposed in parallel with said plurality of reversible Josephson devices. the condition of said circuit being such that upon activation of any one of said signal means. the current transferred into said inductance is sufficient to switch said resettable Josephson junction into its voltage state so as to produce an output signal in said transmission line and that said resettable junction switches back to the zero voltage state when said input signal ceases. in accordance with the criteria:

to ensure reversibility of said input circuit. where 1r.and

UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3, 891, 864

DATED June 24, 1975 INVENTOR(S) 1 Pierre L. Gueret it is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Claim 2, column 11, third formula, after "for N 1" insert for said output circuit-- Claim 3, column 12, line 12, "Elk" should be 1r/A Signed and Sealed this fourth Day Of November 1975 [sum] Allesf.

RUTH C. MASON Arresting Officer C. MARSHALL DANN (ommissimur oj'farems and Trademarks 

1. A Josephson junction logic circuit comprising an output circuit having at least a single resettable Josephson device connected to a transmission line which is terminated with its characteristic impedance and having an input circuit coupled to said device, said output circuit having parameters which meet the following criteria:
 2. A Josephson junction logic circuit according to claim 1, further including another inductance connected in parallel with said input circuit, the current through said input circuit controlling said at least a resettable Josephson junction, both of said inductances being connected to a source of bias current, said input circuit and said another inductance having parameters such that, in the absence of a signal from said signal means, said bias current is divided between said inductances resulting in a control current sufficient to keep said resettable Josephson junction in its voltage state, thereby generating an output in said transmission line and, such that, upon application of a signal from said signal means, current in said input circuit is reduced to a value insufficient to maintain said resettable Josephson junction in its voltage state, causing said resettable Josephson junction to switch to its zero voltage state, thereby eliminating an output signal in said transmission line and wherein the logic circuit parameters to ensure reversibility meet the conditions:
 3. A Josephson logic circuit according to claim 1, wherein said input circuit includes a plurality of reversible Josephson devices electrically connected therein, a plurality of signal means each one of said signal means being electrically coupled to a reversible Josephson junction device, at least an inductance electrically connected to said plurality of reversible Josephson devices, said inductance having a value that, at least in the fundamental mode, where N 0, only less than one flux quantum can be trapped by said inductance and wherein Ibo/imo< pi 1 lambda where Ibo is the bias current supplied to said reversible junctions, lambda is proportional to the inductance L and, N is the maximum number of flux quanta, phi o, which can be trapped in the inductance.
 4. A Josephson logic circuit according to claim 3, wherein said plurality of reversible Josephson devices are disposed in parallel in said input circuit, and said inductance is connected in parallel with said plurality of reversible Josephson devices, and has a value such that the current flowing therethrough when all of said plurality of signal means are energized assumes a magnitude sufficient to switch said at least a single resettable Josephson junction under the conditions:
 5. A Josephson logic circuit according to claim 3, wherein said plurality of reversible Josephson devices are disposed in series in said input circuit and said inductance is disposed in parallel with said plurality of reversible Josephson devices, the condition of said circuit being such that upon activation of any one of said signal means, the current transferred into said inductance is sufficient to switch said resettable Josephson junction into its voltage state so as to produce an output signal in said transmission line and that said resettable junction switches back to the zero voltage state when said input signal ceases, in accordance with the criteria: 